1. Field of the Invention
The present invention relates to a semiconductor device.
2. Related Art
In field effect transistors (FETs) such as a lateral power metal oxide semiconductor field effect transistor (MOSFET) having a source electrode on a back surface (a back surface source), a thickness of an effective epitaxial layer (hereinafter referred to as “effective epitaxial thickness”) is considerably influential on a drain-source breakdown voltage (BVdss) and a drain-source capacitance (Cds), and it is preferable to have thicker effective epitaxial thickness to increase the drain-source breakdown voltage and reduce the drain-source capacitance.
Further, a diffusion of an impurity into a substrate is often conducted in order to contact the source with the back surface of the substrate, while an unwanted extending of the substrate is occurred by the diffusion of the impurity, thereby reducing the effective epitaxial thickness. The reason for contacting the source with the back surface of the substrate is that, when a wire is coupled thereto from a source electrode on the front surface side of the substrate, a source inductance generated by the wire considerably deteriorates the radio frequency (RF) characteristics, and under such circumstance, a source electrode is provided on the back surface thereof to provide a direct coupling of the back surface of the substrate to a package frame.
Accordingly, it is critical for inhibiting the extending of the substrate to provide a thicker effective epitaxial thickness, while diffusing an impurity into the substrate to provide a contact between the source and the back surface of the substrate. It is also critical to reduce a resistance of the substrate to the utmost.
In conventional techniques, which are typically represented by techniques described in Japanese Patent Laid-Open No. 2004-063,922 and Japanese Patent Laid-Open No. 2002-343,960, a field effect transistor (FET) such as an N-channel lateral MOSFET comprises a P− epitaxial layer 11 on a P+ substrate 10, as shown in a cross-sectional view of FIG. 7, and a field effect transistor structure such as MOSFET and the like, which typically includes an N+ source diffusion layer 15, an N− drain layer 16 and a gate electrode 17, are formed thereon. Here, the N+ source diffusion layer 15 is coupled to a P+ buried layer 12a through a source electrode 18. The P+ buried layer 12a is coupled to the P+ substrate 10 to form a back surface source-grounding structure.
The P+ buried layer 12a for forming the back surface source-grounding structure can be formed by, as shown in cross-sectional process views of FIGS. 8A to 8D, growing the P− epitaxial layer 11 on the P+ substrate 10 (FIGS. 8A and 8B), and thereafter conducting a diffusion or an ion implantation of P+ for forming P+ buried layer 12a (FIG. 8C), and then thermally processing thereof for forming a buried structure (FIG. 8D).